The work described here was supported by the National Science Foundation, under grant SER 76-14494.
This information is NOT copyrighted. Permission is given to copy this information and to distribute it to any interested parties.
ASSIST-V is an extension to the ASSIST package. ASSIST was developed at Penn State for use by students in assembler language programming classes. ASSIST-V extends the capabilities of ASSIST to enable students in operating systems courses to handle interrupts, to execute privileged instructions, and to execute channel programs.
To use this guide, you should already be familiar with standard ASSIST. A brief review of some ASSIST pseudo-instructions is given here, and full details on them may be found in the ASSIST Introductory Assembler User's Manual [5]. An introduction to the features of ASSIST-V is given in ASSIST-V: An Environment Simulator for IBM 360 Systems Software Development [2]. Another document that you may need to consult is the IBM S/360 Principles of Operation [4], which gives information on the hardware of the S/360; that material will be assumed in this guide. People interested in bringing up an ASSIST-V system should consult the ASSIST-V PLM [3], as well as the ASSIST PLM [6] and the ASSIST System Distribution Writeup [1].
The user of ASSIST-V prepares an "operating system" and a series of one or more test programs for that system. The term "operating system" in this context means one or more supervisory routines to oversee the execution of the test program. The supervisory routine may be as simple as the interrupt handler for a single type of interrupt, or it may be as complex as a multiprogramming operating system. The operating system might even be a loader program that reads the test programs from the input stream, or the loader might read an operating system that in turn reads test programs.
This operating system and its test program(s) are submitted to ASSIST-V for assembly and execution. ASSIST-V assembles the operating system and relocates the resultant object code as if it were placed beginning at location 0 of an IBM 360. The operating system should include code to define the reserved storage locations for new PSW's for each interrupt type being handled. An initial value should also be assigned for the interval timer at location X'50', if timer services are used by the operating system. The user must also provide an initial value for the PSW showing where execution should begin within the operating system, and with what status (protection key and mask values). The initial PSW must be at location 0 of the user's operating system.
After assembling the program submitted, ASSIST-V prepares for a simulation run. The size of the simulated machine is determined to be the smallest multiple of 2K (2048) greater than or equal to the length of the program assembled. ASSIST-V then fills all uninitialized storage locations (e.g. areas declared by DS statements) with X'F7', fills all registers with X'F6', and assigns each 2K byte memory block a protection key of 0, with fetch protection applied.
To begin the simulation, ASSIST-V fetches the contents of location 0 and makes this the active value of the PSW. It then procedes to fetch and interpret instructions, simulating their effects as described in [4]. In the event of a program exception (e.g. invalid opcode, protection violation, address out of range, etc.), the active PSW is stored at the program old PSW reserved location (X'28') and the contents of the program new PSW location (X'68') are made active. This action differs from that of regular ASSIST, in that ASSIST would normally terminate a user for such a violation, while ASSIST-V effects a program interruption. Under ASSIST-V execution proceeds using the PSW specified in the program interrupt new PSW.
ASSIST-V contains a table of the execution time for each machine instruction or I/O operation. After an instruction is performed or an I/O operation occurs, the contents of the interval timer (memory location X'50') are decremented accordingly. If the interval timer passes from zero to negative, an external interruption is signalled, and whenever the external interrupt bit (bit 7) of the PSW permits external interrupts, the storing of an old and fetching of a new PSW occurs.
The completion of an I/O activity, and also other conditions in I/O execution, signal I/O interruptions. The PSW swaps for these are controlled by the system mask, bits 0-6 of the PSW. The interruption mechanism is the same as described above for program and external interrupts.
ASSIST-V continues to simulate instruction execution until one of three events occurs:
After the program terminates, ASSIST-V displays final statistics about the simulation. These include length of the simulation in timer units, percent of time the CPU and each channel were active, and percent of overlap by the processors.
If the simulation terminated abnormally (reason 2 or 3 above), or if the user requested a dump (XOPC 25), a termination dump is printed. This includes the final value of the PSW, a trace of the last 10 instructions, a trace of the last 10 branches and/or PSW swaps, and the final contents of the registers and memory of the simulated machine.
Most of the ASSIST pseudo-instructions are implemented under ASSIST-V, although the interpretation of a few of them has been changed. This section contains a brief description of the principal pseudo-instruction.
The pseudo-instructions in this section are listed primarily for review; anyone who wants more information on the forms or meaning of the instructions should consult [5] for specific information.
For converting numbers between binary and decimal, the XDECI and XDECO instructions are used.
[label] XDECI reg,addr
[label] XDECO reg,addr
These instructions convert from external (EBCDIC) representations of decimal numbers to binary (XDECI) and from binary to EBCDIC decimal (XDECO). The binary value is placed in or taken from the register designated as reg, and the source or destination for the decimal data is at the address specified as addr. The operand addr may be any legal RX-type second operand, e.g., LABEL+48, LABEL(5), 0(5,6). The operands are not required to be aligned to any particular boundary.
Conversions between hexadecimal and decimal are covered by the XHEXI and XHEXO instructions.
[label] XHEXI reg,addr
[label] XHEXO reg,addr
These instructions are analogous to XDECI and XDECO except that the conversion is to/from EBCDIC representations of hexadecimal values, instead of decimal.
Three instructions are provided for simple I/O involving a card reader, a line printer and a card punch.
[label] XREAD addr,len
[label] XPRNT addr,len
[label] XPNCH addr,len
These commands cause reading of a card from the standard reader, printing of a line on the standard (source listing) printer, and punching of a card on the standard punch. Each execution of one of these uses a new card or a new line. For XREAD the EBCDIC form of the data on the card is transferred to the storage locations beginning at address addr, and continuing for len bytes. Additionally, XREAD sets the condition code 0 to indicate successful read, and 1 to indicate end of file. For XPRNT and XPNCH, the len bytes beginning at memory location addr are printed or punched as the next record. The operands are not required to be aligned to any particular boundary.
There is also one instruction, which has two forms, useful for displaying values for debugging.
[label] XDUMP
[label] XDUMP addr,len
The first form of this instruction, without any operands, causes the contents of the registers to be printed on the standard printer. If the second form is used, the contents of len bytes of memory beginning at address addr are dumped in hexadecimal. The operands are not required to be aligned to any particular boundary.
In addition to the pseudo-instructions, ASSIST and ASSIST-V accept a series of calls to the ASSIST interpreter to perform supervisor services. The calls are provided by XOPC's (eXtended OP Codes). The full list of XOPC's is given below. Those entries preceded by an asterisk (*) are interpreted differently under ASSIST-V than under ASSIST; the ASSIST-V interpretation is given for these. The notation "Not ASSIST-V" indicates an XOPC not accepted under ASSIST-V; execution of one of these results in a condition code setting of 3.
0: (Not ASSIST-V) Set pseudo-SPIE exit address
* 1: Set trace bounds and flags. For execution of this XOPC, registers
0, 1 and 2 must contain the following information:
R0 - lower limit address for tracing (not used on CCW trace)
R1 - upper limit address for tracing (not used on CCW trace)
(Although not used on CCW traces, the address bounds are
nevertheless checked for legality; they must specify proper machine
addresses.)
R2 - flags:| Seeks | CCWs | Interrupts |Instructions|
| Byte 0 | Byte 1 | Byte 2 | Byte 3 |
The flag bits are interpreted as follows.
Byte 0 Meaning
1xxx xxxx ignored
x1xx xxxx trace seeks on channel 1 devices
xx1x xxxx trace seeks on channel 2 devices
xxx1 1111 ignored
Byte 1 Meaning
1xxx xxxx trace each CCW executed on channel 0 devices
x1xx xxxx trace each CCW executed on channel 1 devices
xx1x xxxx trace each CCW executed on channel 2 devices
xxx1 1111 ignored
Byte 2 Meaning
1xxx xxxx trace all PSW swaps
x1xx xxxx trace all I/O interruptions
xx1x xxxx trace all external interruptions
xxx1 xxxx trace all SVC interruptions
xxxx 1xxx trace all program interruptions
xxxx x1xx ignored
xxxx xx1x trace PSW swaps occurring only in supervisor state
xxxx xxx1 trace PSW swaps occurring only in problem state
(Note: if the last two bits are 00 or 11, they have
no effect. If they are 10 or 01, the system state
tested is that in the old PSW, i.e., the state in
effect at the time of the interruption.)
Byte 3 Meaning
1xxx xxxx trace all CPU instructions executed
x1xx xxxx trace all privileged instructions
xx1x xxxx trace all instructions that modify memory
xxx1 xxxx trace all branch-type instructions and LPSW's
xxxx 11xx ignored
xxxx xx1x trace instructions only in supervisory state
xxxx xxx1 trace instructions only in problem state
(Note: if bit 0 is "1", then bits 1, 2 and 3 are
ignored.)
2: Turn on trace facility. (Must have been preceded by an XOPC 1 or
XOPC 3 to set trace bounds and flags.)
3: Set bounds and turn on trace facility. This XOPC is the logical
equivalent of XOPC 1 and XOPC 2. Registers are set as in XOPC 1.
4: Turn off trace facility. (Bounds and flags are retained, so that
the same tracing may be reactivated by executing an XOPC 2).
5: Set addresses for storage modification check.
6: Turn on storage modification check.
7: Set addresses and turn on storage modification check.
8: Turn off storage modification check.
9: (Not ASSIST-V) Turn on boundary alignment check.
10: (Not ASSIST-V) Turn off boundary alignment check.
11: Fetch count of remaining instructions. After execution of this
XOPC, R0 will contain the number of instructions that may still be
executed before ASSIST will terminate the user's program.
12: (Not ASSIST-V) Emulate S/360. Execution of this instruction will
cause only the S/360 instruction set to be interpreted.
13: (Not ASSIST-V) Emulate S/370. Execution of this XOPC will cause
the nonprivileged S/370 instructions to be recognized, as well as
the S/360 ones. If ASSIST-V is executing on a S/360, the effect of
the S/370 instructions will be simulated using only S/360 ones.
*14: Halt or interrupt after n instructions are simulated. Register 0
contains the value for n. If XOPC 15 is not encountered before n
more instructions are simulated, then the program will terminate
after the n-th instruction. If XOPC 15 is encountered before n
more instructions are performed, then a console interrupt will be
raised.
*15: Turn on console interrupt facility. If XOPC 14 has not been
previously executed, then this instruction has no meaning. If XOPC
14 has been previously executed, an external interruption will
occur after n instructions are executed (counting from the XOPC
14). The interrupt code portion of the old PSW will show the
console as the source of the interrupt. (i.e., bits 16-31 will
contain B'xxxx xxxx x1xx xxxx'.)
16: Turn on instruction execution count (IECF) facility. This produces
a profile of the number of times each instruction in the program is
executed.
17: Set address bounds for the IECF facility.
18: Set address bounds and turn on the IECF facility.
19: Turn off the IECF facility.
20: Clear the IECF facility counting area.
21: (Not ASSIST-V) Return from handling a pseudo-SPIE.
22: Dump statistics gathered by the IECF facility.
*23: Get current simulated wall clock time. The simulated time is
returned in register 0.
*24: Halt ASSIST-V simulation normally.
*25: Halt ASSIST-V simulation abnormally (with a dump printed).
All XOPC codes greater than 25 are invalid. If any of these is executed, or if one of the "Not ASSIST-V" XOPC's is executed under ASSIST-V, then the condition code is set to 3. Further information on the XOPC's may be found in [5], section IV.
In addition to the pseudo-instructions that permit I/O, ASSIST-V simulates the execution of channel commands (CCW's) to a variety of devices. The execution of CCW's progresses effectively via the normal S/360 I/O command execution cycle. This cycle is outlined briefly below, and more details may be found in [4].
The user prepares a channel program consisting of one or more channel commands. The address of the first CCW is placed in the Channel Address Word (CAW), which is at fixed memory location X'48'. The CAW occupies a full word. The low order (rightmost) three bytes contain the address of the channel program to be executed; the high order byte contains the protection key under which data transfer is to occur.
The user then executes the privileged instruction SIO, Start I/O. The operand field of this instruction identifies the address of the device selected for I/O. If the SIO is accepted and the channel program is commenced, then the condition code is set to 0 and control returns to the user. If there is an error sensed in the channel program before its execution begins, then the condition code is set to 1 and the Channel Status Word (CSW) is stored in the doubleword at location X'40'. The CSW indicates the type of error detected. If the device addressed does not exist, the condition code is set to 3.
Once the channel program has been accepted, it progresses in parallel with CPU operation, fetching new CCW's and fetching or storing data in memory as needed. When the last CCW has been completed, or when an abnormal situation is sensed during I/O operation, an interruption is signalled. If the system mask bit for the signalling channel is 1, then an I/O interruption is effected; else the interruption is held pending until the system mask bit is set to 1. When the interruption is effected, the old PSW indicates the device address of the interrupting device, and the CSW is stored to identify the cause of the interruption. If two interruptions are pending for the same device, the earlier one is eliminated. If two or more devices on the same channel have interruptions pending simultaneously, the one for the lower numbered device is taken first.
Whenever an interrupt occurs, the channel causes the CSW in fixed memory location X'40' to be updated. The CSW is the analog of the PSW for I/O operations. It identifies the address of the next CCW to be executed (the address 8 bytes higher than the address of the current CCW), the protection key value under which data transfer was occurring, the amount of the count residue, which is the number of bytes left untransferred from the amount requested in the last CCW, and status bits. The status bits are interpreted under ASSIST-V as follows. (Note that the interpretation under ASSIST-V differs slightly from the standard interpretation.)
Identification Bit Meaning
Attention X'8000' attempted read past end-of-file
Status modifier X'4000' direct access search has succeeded and one
CCW will be skipped
Control unit end X'2000' end of channel activity on direct access
device
Busy X'1000' channel activity in progress for addressed
device
Channel end X'0800' end of channel activity on any device
Device end X'0400' end of channel activity on any device
Unit check X'0200' recognition of improper command after the
command has been accepted. Possible causes:
seek to invalid address or misformed file
mask
Unit exception X'0100' detection of end of file
PCI X'0080' recognition of CCW having PCI (program
controlled interrupt) bit "1". Note: the
interrupt from a PCI occurs immediately
when execution commenced of a CCW having
bit 36=1
Incorrect length X'0040' execution of CCW having count field other
than proper length for device: 80 for card
reader, 132 for printer, amount specified
in count area for direct access record
Program check X'0020' improperly formed channel program. Possible
causes include CCW not on doubleword bound-
ary, CCW with count field of 0, TIC as first
CCW of program, TIC whose address specifies
another TIC, improper operation code.
Protection check X'0010' protection violation detected during CCW
execution. Possible causes: source address
of next CCW fetch protected, address of data
field for write, search, set file mask fetch
protected, or address of data for read store
protected; all performed with key from CAW
that does not match key of memory to be
accessed.
unused X'000F'
The distributed version of ASSIST-V has a default group of devices as listed below. See [3] for more information on how to change this set of devices.
Device Address Type DDNAME
X'00C' reader VIRTRDR1
X'00D' reader VIRTRDR2
X'00E' printer VIRTPRT1
X'00F' printer VIRTPRT2
X'101' disk VIRTDSK1
X'201' drum VIRTDRM1
Channel 0 is a multiplexor channel supporting card readers and printers. The default set of devices includes two readers and two printers.
The readers process 80 character card images at a speed of 200 msec. per card. The only command acceptable for the readers is X'02': read, feed, and select stacker 1.
The printers process 132 character line images. Processing time for the printer is composed of two factors: data transfer time and carriage movement time. Carriage movement is calculated as 30 msec. startup time, plus 5 msec. for each line spaced. Data transfer requires 165 msec. for all or part of a line printed.
Exec. time
Command (msec.) Meaning
X'01' 165 write, no space after print
X'09' 205 write, space 1 after print
X'0B' 35 skip 1 line immediately
X'11' 210 write, space 2 after print
X'13' 40 skip 2 lines immediately
X'19' 215 write, space 3 after print
X'1B' 45 skip 3 lines immediately
X'89' 265 write, skip to channel 1 after print
X'8B' 100 skip to channel 1 immediately
The remaining devices simulated by ASSIST-V are direct access devices, disks and drums. The arrangement of data on the recording surfaces of these devices is the same, as are the majority of commands used to program these devices.
The primary unit of data on a direct access device is a track. Figure 1 below shows the form of a track.
---------- ----------- ------- --------
X G | Home | G | Count | G | Key | G | Data | G ---+
XXX 1 | Address| 2 | Area | 2 | Area| 2 | Area | 3 |
---------- ----------- ------- -------- |
Index ( ========== Record R0 =========== ) |
|
+-----------------------------------------------------------------+
|
| --------- ------- ------- ---------
+-> | Count | G | Key | G | Data| G | Count | ..etc.. ---+
| Area | 2 | Area| 2 | Area| 3 | Area | |
--------- ------- ------- --------- |
( ========= Record 1 ========== ) ( === Record 2 ... |
|
+-----------------------------------------------------------------+
|
--------- ------- ------
+-> | Count | G | Key | G |Data| G X
| Area | 2 | Area| 2 |Area| 4 XXX
--------- ------- ------
( ======= Last Record ======== ) Index
Figure 1: Track Format
The form of data on a track is as follows. Data records may be recorded in either of two formats: count-key-data or count-data format. Each of these begins with an 8 byte count area that specifies the cylinder and head number, the record number on the track, and the lengths of the key and data fields of the record. For count-key-data records, a key area is present and the length of the key area is given in the count area. For count-data records, no key area exists, and the key length portion of the count area contains 0. The key (if present) and data portions of a record follow the count field.
Each of the count, key, and data areas is separated from the others by a gap, called a G2 gap, which is 6 bytes long. Each record except R0 is separated from the previous record by an 8 byte G3 gap. The last record on the track is followed by a variable-length gap, called the G4 gap. This gap must be at least 8 bytes long, and consists of the remaining space on the track.
The first record on a track is called R0, or the capacity record. This record is of count-data format, and is accessed by special commands, read R0 and write R0. This record is frequently used to maintain a count of free space remaining on the track.
Each track has a mark called the "index point", followed by an 8 byte gap and then the address, that indicates the track number and the head number. The home address marks the beginning of the track.
Channel 1 supports one disk device, at device address X'101'. The disk has four recording surfaces, each of which contains twenty tracks. The capacity of a track is 1692 bytes, but because of required gap areas, the full 1692 bytes is not available for recorded data. The total capacity of a disk unit, including gap space, is 135,360 bytes. Recorded data is transferred at an approximate rate of 76,800 characters per second. The access mechanism takes approximately 2 msec. per cylinder crossed.
Channel 2 supports a fixed-head drum-like device, at address X'201'. The unit has twenty tracks of 2048 bytes each, for a total device capacity of 40,960 bytes. Again, because of gaps, this full area may not be filled with user data. The transfer rate for this device is 122,880 bytes per second. There is no head movement.
Commands on direct access devices fall into five general categories:
Control commands - TIC (branch within a channel program) and Set File Mask (permit or inhibit writing and head movement)
Seek - activate a different head and/or move access mechanism to a different track
Search - compare part of the current record against a specified value in main memory.
Read - transfer data from the device to main memory
Write - transfer data from main memory to the device
Channel commands that may be used for direct access devices are shown below.
Command
Code Command Meaning
X'-8' TIC branch within channel program
(First 4 bits of TIC command ignored)
X'1F' Set file mask set file mask from specified
main storage address
X'07' Seek position access mechanism/select head
X'08' Seek cylinder position access mechanism
X'18' Seek head select head
X'29' Search key equal compare next key on track with
X'49' Search key high key in main storage
X'69' Search key high/equal
X'31' Search ID equal compare cylinder/head/record number
X'51' Search ID high in next count area on track
X'71' Search ID high/equal with values in main storage
X'39' Search home address compare cylinder/head number in
equal home address on track with
value in main storage
X'06' Read data read data field of next record
X'0E' Read key-data read key-data fields of next record
X'12' Read count read count field of next record
X'16' Read record R0 read count-key-data fields of R0
X'1E' Read count-key-data read count-key-data fields of next
record
X'05' Write data write data field of next record
X'0D' Write key-data write key-data fields of next record
X'15' Write record R0 write count-key-data fields of R0
X'1D' Write count-key-data write count-key-data fields of next
record
CONTROL COMMANDS
TIC The data address field of this instruction specifies the address of the next CCW to be fetched. Program check condition is raised if an invalid address is specified (not a doubleword boundary) or if one TIC chains to another. Bits 0-3 and 32-63 are ignored. If a command is data chained to a TIC, the TIC specifies the address of a CCW whose data address, flags and count are used with the operation code of the old instruction; if a command is command chained to a TIC, the TIC specifies the address of a CCW whose full operation code, flags, data address and count are used.
Set File Mask The data address of this command identifies one byte in main storage. The bits of that byte are used to set write and head movement inhibitions.
Mask Meaning
B'000xxx0x' inhibit write R0
B'010xxx0x' inhibit all write commands
B'100xxx0x' inhibit format writes (write R0 and write count-key-data)
B'110xxx0x' permit all writes
B'xx000x0x' permit all seek commands
B'xx001x0x' permit seek cylinder and seek head
B'xx010x0x' permit seek head
B'xx011x0x' inhibit all seek commands
Notice that bits 2 and 6 must be zero, or unit check condition is raised. Set file mask is allowed only once within a CCW chain. Initial setting of the file mask is B'00000000'.
SEEKS
Seek commands are used to position the access mechanism to a desired cylinder and to activate the desired head. Seek commands are limited by the current file mask in effect (see the Set File Mask instruction). The commands normally transfer a 6 byte field specifying cylinder and head number as follows:
X'00 00 00 CC 00 HH'
where CC identifies the cylinder and HH identifies the head. CC and HH must not exceed the sizes for the device; if they do, or if any of the other bytes is nonzero, the seek is aborted and unit check condition is raised. A CCW count of 6 is normal. If a count greater than 6 is specified, only the first 6 bytes at the specified address are used; if a count less than 6 is specified, unit check condition is raised.
Seek positions access mechanism and selects head.
Seek Cylinder positions access mechanism without head selection. The full seek address (both cylinder and head number) must be valid; however, only the cylinder addess is used.
Seek Head activates a head without moving the access mechanism. The full seek address (both cylinder and head number) must be valid; however, only the head number is used.
SEARCHES
Search commands cause comparison between recorded information on a device and infomation from main storage. The address field of the CCW specifies the main storage address of the field to be compared; the count field in the CCW determines the length to be compared. The comparison is logical, proceeding one byte at a time, left to right.
If the search succeeds (i.e., the data on the device is equal to [ or higher than, as requested ] the data in main memory), the status modifier bit is set in the CSW. If command chaining is in effect, the status modifier causes one CCW to be skipped. (The next CCW fetched for execution is at the address 16 bytes higher than that of the search CCW.)
If the search fails and command chaining is in effect, the immediately following CCW is executed next. This CCW is often a TIC back to the search to force comparison to subsequent records on the same track. However, if the index point of the track is sensed twice in such a sequence of searches, the command sequence is halted, with the CSW showing device end and channel end. (Two index points guarantee at least one full revolution of the device.)
A mode of search called "multitrack searching" may also be specified. This is specified by setting the leftmost bit of the command code "1"; i.e., X'A9' is the multitrack mode of the search key equal command, which normally has code X'29'. In multitrack mode each time the index point is sensed, the next higher numbered head is selected. When no higher numbered head exists, the search terminates with channel end and device end. Using multitrack searches, it is possible to compare all records on a cylinder, instead of on only one track.
The search CCW may have a count field longer than the data recorded on the track. Only the number of bytes existing on the track are compared, however; those bytes compared from main storage are the first ones from the area.
The search may have a count field shorter than the data recorded on the track. In this case only the number of bytes in the CCW are compared. Action occurs as for full length comparisons. However, write commands that need to be chained from a successful search may be chained only from a search which compared the full field of data recorded on the device.
Search Key compares an area in main storage with the next key on the track. The length is either the length in the CCW or the length of the actual key field, whichever is shorter. Search succeeds if the key on the track is equal to, higher than, or higher than or equal to the key in main storage.
Search ID compares a five byte area in main storage with the cylinder, head, and record number of count field of next record. The main storage area should contain
X'00 CC 00 HH RR'
where CC is the cylinder number, HH is the head number, and RR is the record number. Search succeeds if the count field on the track is equal to, higher than, or higher than or equal to the data in main storage.
Search Home Address compares a four byte area in main storage with the cylinder and head number of the current track, as written in the home address record. Thus, an implicit positioning of the device to the home address of the track occurs. The main storage area should contain data of the form
X'00 CC 00 HH'
where CC is the cylinder number and HH is the head number. Search succeeds if the home address on the track is equal to, higher than, or higher than or equal to the data in main storage.
READS
Reads transfer data from direct access device to main memory. The maximum amount of data transferred is the smaller of the amount specified in the CCW count field and the amount specified in the key length/data length on the track. Any record for which the key length and data length fields are both zero is recognized as an end-of-file record. Reading such a record raises a unit exception condition.
Read R0 transfers count, key and data areas of R0. This command causes positioning to the R0 record.
Read Count transfers the count field of any record (except R0) from disk to main memory. The normal length for this command is eight. The information passed is of the following form.
X'00 CC 00 HH RR KL DD LL'
where CC is the cylinder number, HH is the head number, RR is the record number, KL is the key length, and DD LL is the data length field.
Read Count-Key-Data transfers all fields of the next record encountered on the track.
Read Data transfers the next data field encountered on the track.
Read Key-Data transfers the next key and data fields encountered on the track. If the key length is zero, the command operates as a Read Data command.
WRITES
Write commands are of two groups: format writes and nonformat writes. Format writes are ones in which the count field is rewritten. Format writes rewrite the specified record; furthermore, the entire rest of the track is filled with 0's. The CCW count for a format write must be at least 8.
Nonformat writes do not modify the count field on the device. Thus, the key length and data length portions of the record are unchanged, and must represent the true key length and record length of the rewritten record. For this reason if the key length or data length is longer on the track than the amount of data indicated in the CCW count field, the remaining area on the track within the current record is padded with 0's. If the key length or data length on the track is smaller than the amount of data indicated in the count of the CCW, only the amount of data specified in the count field on the track is written.
For positioning reasons, certain chaining requirements are shown. The search command from which the write is chained must examine the full area that it compares; it may not have a CCW length field smaller than the length of the ID or key that is being examined. Also the setting of the file mask must permit the type of write being done. These must be met, or the command will be rejected and a unit check condition will be raised.
Write Data updates the next data field encountered on the track. This command must be chained from a successful Search ID Equal or Search Key Equal command.
Write Key and Data updates the next key and data fields encountered on the track. This command must be chained from a successful Search ID Equal command.
Write R0 specifies that a count, key, and data record for R0 is to be written. This command must be chained from a successful Search Home Address Equal command. The count in the CCW must be at least 8.
Write Count Key Data specifies that a count, a key and a data field are to be written on the track. Any information following the record written is lost, for the entire remainder of the track is filled with 0's. The command must be chained from a successful Write R0, Write Count Key Data, Search ID Equal or Search Key Equal. However, a Read Data or Read Key and Data command may be inserted between the search CCW and the Write Count Key Data.
[1] --- ASSIST System Distribution Writeup
[2] Hughes and Pfleeger, ASSIST-V: An Environment Simulator for IBM 360
Systems Software Development.
[3] Hughes and Pfleeger, ASSIST-V PLM.
[4] IBM, S/360 Principles of Operation.
[5] Mashey, ASSIST Introductory Assembler User's Manual.
[6] Mashey, ASSIST PLM.