0 ASSIST-V User's Guide Charles E. Hughes Charles P. Pfleeger CS-77-24 January 1978 The work described here was supported by the National Science Foundation, under grant SER 76-14494. 7 1 1 1 0 ASSIST-V USER'S GUIDE¶ 0 I. FOR WHOM IS THIS GUIDE INTENDED? 0 ASSIST-V is an extension to the ASSIST package. ASSIST was 0 developed at Penn State for use by students in assembler language 0 programming classes. ASSIST-V extends the capabilities of ASSIST to 0 enable students in operating systems courses to handle interrupts, to 0 execute privileged instructions, and to execute channel programs. 0 To use this guide, you should already be familiar with standard 0 ASSIST. A brief review of some ASSIST pseudo-instructions is given 0 here, and full details on them may be found in the ASSIST Introductory 0 Assembler User's Manual [5]. An introduction to the features of 0 ASSIST-V is given in ASSIST-V: An Environment Simulator for IBM 360 0 Systems Software Development [2]. Another document that you may need to 0 consult is the IBM S/360 Principles of Operation [4], which gives 0 information on the hardware of the S/360; that material will be assumed 0 in this guide. People interested in bringing up an ASSIST-V system 0 should consult the ASSIST-V PLM [3], as well as the ASSIST PLM [6] and 0 the ASSIST System Distribution Writeup [1]. 0 II. USING ASSIST-V 0 A. Initial Machine Configuration 0 The user of ASSIST-V prepares an "operating system" and a series of _________________________ ¶ This information is NOT copyrighted. Permission is given to copy this information and to distribute it to any interested parties. 1 2 0 one or more test programs for that system. The term "operating system" 0 in this context means one or more supervisory routines to oversee the 0 execution of the test program. The supervisory routine may be as simple 0 as the interrupt handler for a single type of interrupt, or it may be as 0 complex as a multiprogramming operating system. The operating system 0 might even be a loader program that reads the test programs from the 0 input stream, or the loader might read an operating system that in turn 0 reads test programs. 0 This operating system and its test program(s) are submitted to 0 ASSIST-V for assembly and execution. ASSIST-V assembles the operating 0 system and relocates the resultant object code as if it were placed 0 beginning at location 0 of an IBM 360. The operating system should 0 include code to define the reserved storage locations for new PSW's for 0 each interrupt type being handled. An initial value should also be 0 assigned for the interval timer at location X'50', if timer services are 0 used by the operating system. The user must also provide an initial 0 value for the PSW showing where execution should begin within the 0 operating system, and with what status (protection key and mask values). 0 The initial PSW must be at location 0 of the user's operating system. 0 After assembling the program submitted, ASSIST-V prepares for a 0 simulation run. The size of the simulated machine is determined to be 0 the smallest multiple of 2K (2048) greater than or equal to the length 0 of the program assembled. ASSIST-V then fills all uninitialized storage 0 locations (e.g. areas declared by DS statements) with X'F7', fills all 0 registers with X'F6', and assigns each 2K byte memory block a protection 0 key of 0, with fetch protection applied. 1 3 0 B. Simulated Execution 0 To begin the simulation, ASSIST-V fetches the contents of location 0 0 and makes this the active value of the PSW. It then procedes to fetch 0 and interpret instructions, simulating their effects as described in 0 [4]. In the event of a program exception (e.g. invalid opcode, 0 protection violation, address out of range, etc.), the active PSW is 0 stored at the program old PSW reserved location (X'28') and the contents 0 of the program new PSW location (X'68') are made active. This action 0 differs from that of regular ASSIST, in that ASSIST would normally 0 terminate a user for such a violation, while ASSIST-V effects a program 0 interruption. Under ASSIST-V execution proceeds using the PSW specified 0 in the program interrupt new PSW. 0 ASSIST-V contains a table of the execution time for each machine 0 instruction or I/O operation. After an instruction is performed or an 0 I/O operation occurs, the contents of the interval timer (memory 0 location X'50') are decremented accordingly. If the interval timer 0 passes from zero to negative, an external interruption is signalled, and 0 whenever the external interrupt bit (bit 7) of the PSW permits external 0 interrupts, the storing of an old and fetching of a new PSW occurs. 0 The completion of an I/O activity, and also other conditions in I/O 0 execution, signal I/O interruptions. The PSW swaps for these are 0 controlled by the system mask, bits 0-6 of the PSW. The interruption 0 mechanism is the same as described above for program and external 0 interrupts. 1 4 0 C. Termination of a User Program 0 ASSIST-V continues to simulate instruction execution until one of 0 three events occurs. 0 1. The user halts the simulation by executing an XOPC 24 or XOPC 25. 0 (See the description of XOPC's in section III B. below.) 0 2. The simulation halts due to exceeding the limit for real execution 0 time, number of instructions executed, or amount of output 0 produced. 0 3. The user enters an "interminable wait" state. An interminable wait 0 is one in which 0 (a) the CPU is in wait state (bit 14 of the active PSW is '1'), 0 and (b) no external interrupt can occur "reasonably" soon (the 0 interval timer contains a negative value or the external 0 interrupt mask in the PSW contains a '0'), 0 and (c) no I/O interruptions can occur (either no channel-level I/O 0 is in progress, or the system mask bits for all active 0 channels contain '0'). 0 After the program terminates, ASSIST-V displays final statistics 0 about the simulation. These include length of the simulation in timer 0 units, percent of time the CPU and each channel were active, and percent 0 of overlap by the processors. 0 If the simulation terminated abnormally (reason 2 or 3 above), or 0 if the user requested a dump (XOPC 25), a termination dump is printed. 0 This includes the final value of the PSW, a trace of the last 10 0 instructions, a trace of the last 10 branches and/or PSW swaps, and the 0 final contents of the registers and memory of the simulated machine. 1 5 0 III. PSEUDO-INSTRUCTIONS 0 Most of the ASSIST pseudo-instructions are implemented under 0 ASSIST-V, although the interpretation of a few of them has been changed. 0 This section contains a brief description of the principal 0 pseudo-instruction. 0 A. ASSIST I/O and Conversion Pseudo-Instructions 0 The pseudo-instructions in this section are listed primarily for 0 review; anyone who wants more information on the forms or meaning of the 0 instructions should consult [5] for specific information. 0 For converting numbers between binary and decimal, the XDECI and 0 XDECO instructions are used. 0 [label] XDECI reg,addr [label] XDECO reg,addr + _____ ___ ____ _____ ___ ____ 0 These instructions convert from external (EBCDIC) representations of 0 decimal numbers to binary (XDECI) and from binary to EBCDIC decimal 0 (XDECO). The binary value is placed in or taken from the register 0 designated as reg, and the source or destination for the decimal data is + ___ 0 at the address specified as addr. The operand addr may be any legal + ____ ____ 0 RX-type second operand, e.g., LABEL+48, LABEL(5), 0(5,6). The operands 0 are not required to be aligned to any particular boundary. 0 Conversions between hexadecimal and decimal are covered by the 0 XHEXI and XHEXO instructions. 0 [label] XHEXI reg,addr [label] XHEXO reg,addr + _____ ___ ____ _____ ___ ____ 0 These instructions are analogous to XDECI and XDECO except that the 0 conversion is to/from EBCDIC representations of hexadecimal values, 1 6 0 instead of decimal. 0 Three instructions are provided for simple I/O involving a card 0 reader, a printer and a card punch. 0 [label] XREAD addr,len + _____ ____ ___ [label] XPRNT addr,len + _____ ____ ___ [label] XPNCH addr,len + _____ ____ ___ 0 These commands cause reading of a card from the standard reader, 0 printing of a line on the standard (source listing) printer, and 0 punching of a card on the standard punch. Each execution of one of 0 these uses a new card or a new line. For XREAD the EBCDIC form of the 0 data on the card is transferred to the storage locations beginning at 0 address addr, and continuing for len bytes. Additionally, XREAD sets + ____ ___ 0 the condition code 0 to indicate successful read, and 1 to indicate end 0 of file. For XPRNT and XPNCH, the len bytes beginning at memory + ___ 0 location addr are printed or punched as the next record. The operands + ____ 0 are not required to be aligned to any particular boundary. 0 There is also one instruction, which has two forms, useful for 0 displaying values for debugging. 0 [label] XDUMP [label] XDUMP addr,len + _____ _____ ____ ___ 0 The first form of this instruction, without any operands, causes the 0 contents of the registers to be printed on the standard printer. If the 0 second form is used, the contents of len bytes of memory beginning at + ___ 0 address addr are dumped in hexadecimal. The operands are not required + ____ 0 to be aligned to any particular boundary. 0 B. Extended Operation Codes (XOPC's) 0 In addition to the pseudo-instructions, ASSIST and ASSIST-V accept 0 a series of calls to the ASSIST interpreter to perform supervisor 1 7 0 services. The calls are provided by XOPC's (eXtended OP Codes). The 0 full list of XOPC's is given below. Those entries preceded by an 0 asterisk (*) are interpreted differently under ASSIST-V than under 0 ASSIST; the ASSIST-V interpretation is given for these. The notation 0 "Not ASSIST-V" indicates an XOPC not accepted under ASSIST-V; execution 0 of one of these results in a condition code setting of 3. 0 0: (Not ASSIST-V) Set pseudo-SPIE exit address 0 * 1: Set trace bounds and flags. For execution of this XOPC, registers 0 0, 1 and 2 must contain the following information: 0 R0 - lower limit address for tracing (not used on CCW trace)ý 0 R1 - upper limit address for tracing (not used on CCW trace)ý 0 R2 - flags:| Seeks | CCWs | Interrupts |Instructions| | Byte 0 | Byte 1 | Byte 2 | Byte 3 | 0 The flag bits are interpreted as follows. 0 Byte 0 Meaning + ______ _______ 1xxx xxxx ignored x1xx xxxx trace seeks on channel 1 devices xx1x xxxx trace seeks on channel 2 devices xxx1 1111 ignored Byte 1 Meaning + ______ _______ 1xxx xxxx trace each CCW executed on channel 0 devices x1xx xxxx trace each CCW executed on channel 1 devices xx1x xxxx trace each CCW executed on channel 2 devices xxx1 1111 ignored Byte 2 Meaning + ______ _______ 1xxx xxxx trace all PSW swaps x1xx xxxx trace all I/O interruptions xx1x xxxx trace all external interruptions xxx1 xxxx trace all SVC interruptions xxxx 1xxx trace all program interruptions xxxx x1xx ignored xxxx xx1x trace PSW swaps occurring only in supervisor state xxxx xxx1 trace PSW swaps occurring only in problem state (Note: if the last two bits are 00 or 11, they have _________________________ ý Although not used on CCW traces, the address bounds are nevertheless checked for legality; they must specify proper machine addresses. 1 8 no effect. If they are 10 or 01, the system state tested is that in the old PSW, i.e., the state in effect at the time of the interruption.) Byte 3 Meaning + ______ _______ 1xxx xxxx trace all CPU instructions executed x1xx xxxx trace all privileged instructions xx1x xxxx trace all instructions that modify memory xxx1 xxxx trace all branch-type instructions and LPSW's xxxx 11xx ignored xxxx xx1x trace instructions only in supervisory state xxxx xxx1 trace instructions only in problem state (Note: if bit 0 is "1", then bits 1, 2 and 3 are ignored.) 0 2: Turn on trace facility. (Must have been preceded by an XOPC 1 or 0 XOPC 3 to set trace bounds and flags.) 0 3: Set bounds and turn on trace facility. This XOPC is the logical 0 equivalent of XOPC 1 and XOPC 2. Registers are set as in XOPC 1. 0 4: Turn off trace facility. (Bounds and flags are retained, so that 0 the same tracing may be reactivated by executing an XOPC 2). 0 5: Set addresses for storage modification check. 0 6: Turn on storage modification check. 0 7: Set addresses and turn on storage modification check. 0 8: Turn off storage modification check. 0 9: (Not ASSIST-V) Turn on boundary alignment check. 0 10: (Not ASSIST-V) Turn off boundary alignment check. 0 11: Fetch count of remaining instructions. After execution of this 0 XOPC, R0 will contain the number of instructions that may still be 0 executed before ASSIST will terminate the user's program. 0 12: (Not ASSIST-V) Emulate S/360. Execution of this instruction will 0 cause only the S/360 instruction set to be interpreted. 0 13: (Not ASSIST-V) Emulate S/370. Execution of this XOPC will cause 0 the nonprivileged S/370 instructions to be recognized, as well as 0 the S/360 ones. If ASSIST-V is executing on a S/360, the effect of 1 9 0 the S/370 instructions will be simulated using only S/360 ones. 0 *14: Halt or interrupt after n instructions are simulated. Register 0 0 contains the value for n. If XOPC 15 is not encountered before n 0 more instructions are simulated, then the program will terminate 0 after the n-th instruction. If XOPC 15 is encountered before n 0 more instructions are performed, then a console interrupt will be 0 raised. 0 *15: Turn on console interrupt facility. If XOPC 14 has not been 0 previously executed, then this instruction has no meaning. If XOPC 0 14 has been previously executed, an external interruption will 0 occur after n instructions are executed (counting from the XOPC 0 14). The interrupt code portion of the old PSW will show the 0 console as the source of the interrupt. (i.e., bits 16-31 will 0 contain B'xxxx xxxx x1xx xxxx'.) 0 16: Turn on instruction execution count (IECF) facility. This produces 0 a profile of the number of times each instruction in the program is 0 executed. 0 17: Set address bounds for the IECF facility. 0 18: Set address bounds and turn on the IECF facility. 0 19: Turn off the IECF facility. 0 20: Clear the IECF facility counting area. 0 21: (Not ASSIST-V) Return from handling a pseudo-SPIE. 0 22: Dump statistics gathered by the IECF facility. 0 *23: Get current simulated wall clock time. The simulated time is 0 returned in register 0. 0 *24: Halt ASSIST-V simulation normally. 0 *25: Halt ASSIST-V simulation abnormally (with a dump printed). 1 10 0 All XOPC codes greater than 25 are invalid. If any of these is 0 executed, or if one of the "Not ASSIST-V" XOPC's is executed under 0 ASSIST-V, then the condition code is set to 3. Further information on 0 the XOPC's may be found in [5], section IV. 0 IV. CHANNEL-LEVEL I/O 0 In addition to the pseudo-instructions that permit I/O, ASSIST-V 0 simulates the execution of channel commands (CCW's) to a variety of 0 devices. The execution of CCW's progresses effectively via the normal 0 S/360 I/O command execution cycle. This cycle is outlined briefly 0 below, and more details may be found in [4]. 0 A. Overview of I/O Activity 0 The user prepares a channel program consisting of one or more 0 channel commands. The address of the first CCW is placed in the Channel 0 Address Word (CAW), which is at fixed memory location X'48'. The CAW 0 occupies a full word. The low order (rightmost) three bytes contain the 0 address of the channel program to be executed; the high order byte 0 contains the protection key under which data transfer is to occur. 0 The user then executes the privileged instruction SIO, Start I/O. 0 The operand field of this instruction identifies the address of the 0 device selected for I/O. If the SIO is accepted and the channel program 0 is commenced, then the condition code is set to 0 and control returns to 0 the user. If there is an error sensed in the channel program before its 0 execution begins, then the condition code is set to 1 and the Channel 0 Status Word (CSW) is stored in the doubleword at location X'40'. The 0 CSW indicates the type of error detected. If the device addressed does 1 11 0 not exist, the condition code is set to 3. 0 Once the channel program has been accepted, it progresses in 0 parallel with CPU operation, fetching new CCW's and fetching or storing 0 data in memory as needed. When the last CCW has been completed, or when 0 an abnormal situation is sensed during I/O operation, an interruption is 0 signalled. If the system mask bit for the signalling channel is 1, then 0 an I/O interruption is effected; else the interruption is held pending 0 until the system mask bit is set to 1. When the interruption is 0 effected, the old PSW indicates the device address of the interrupting 0 device, and the CSW is stored to identify the cause of the interruption. 0 If two interruptions are pending for the same device, the earlier one is 0 eliminated. If two or more devices on the same channel have 0 interruptions pending simultaneously, the one for the lower numbered 0 device is taken first. 0 Whenever an interrupt occurs, the channel causes the CSW in fixed 0 memory location X'40' to be updated. The CSW is the analog of the PSW 0 for I/O operations. It identifies the address of the next CCW to be 0 executed (the address 8 bytes higher than the address of the current 0 CCW), the protection key value under which data transfer was occurring, 0 the amount of the count residue, which is the number of bytes left 0 untransferred from the amount requested in the last CCW, and status 0 bits. The status bits are interpreted under ASSIST-V as follows. (Note 0 that the interpretation under ASSIST-V differs slightly from the 0 standard interpretation.) 1 12 Identification Bit Meaning + ______________ ___ _______ Attention X'8000' attempted read past end-of-file Status modifier X'4000' direct access search has succeeded and one CCW will be skipped Control unit end X'2000' end of channel activity on direct access device Busy X'1000' channel activity in progress for addressed device Channel end X'0800' end of channel activity on any device Device end X'0400' end of channel activity on any device Unit check X'0200' recognition of improper command after the + _____ command has been accepted. Possible causes: seek to invalid address or misformed file mask Unit exception X'0100' detection of end of file PCI X'0080' recognition of CCW having PCI (program controlled interrupt) bit "1". Note: the interrupt from a PCI occurs immediately when execution commenced of a CCW having bit 36=1 Incorrect length X'0040' execution of CCW having count field other than proper length for device: 80 for card reader, 132 for printer, amount specified in count area for direct access record Program check X'0020' improperly formed channel program. Possible causes include CCW not on doubleword bound- ary, CCW with count field of 0, TIC as first CCW of program, TIC whose address specifies another TIC, improper operation code. Protection check X'0010' protection violation detected during CCW execution. Possible causes: source address of next CCW fetch protected, address of data field for write, search, set file mask fetch protected, or address of data for read store protected; all performed with key from CAW that does not match key of memory to be accessed. unused X'000F' 0 The distributed version of ASSIST-V has a default group of devices 0 as listed below. See [3] for more information on how to change this set 0 of devices. 1 13 Device Address Type DDNAME + ______________ ____ ______ X'00C' reader VIRTRDR1 X'00D' reader VIRTRDR2 X'00E' printer VIRTPRT1 X'00F' printer VIRTPRT2 X'101' disk VIRTDSK1 X'201' drum VIRTDRM1 0 B. Unit Record Devices - Channel 0 0 Channel 0 is a multiplexor channel supporting card readers and 0 printers. The default set of devices includes two readers and two 0 printers. 0 The readers process 80 character card images at a speed of 200 0 msec. per card. The only command acceptable for the readers is X'02': 0 read, feed, and select stacker 1. 0 The printers process 132 character line images. Processing time 0 for the printer is composed of two factors: data transfer time and 0 carriage movement time. Carriage movement is calculated as 30 msec. 0 startup time, plus 5 msec. for each line spaced. Data transfer requires 0 165 msec. for all or part of a line printed. 0 Exec. time Command (msec.) Meaning + _______ __________ _______ X'01' 165 write, no space after print X'09' 205 write, space 1 after print X'0B' 35 skip 1 line immediately X'11' 210 write, space 2 after print X'13' 40 skip 2 lines immediately X'19' 215 write, space 3 after print X'1B' 45 skip 3 lines immediately X'89' 265 write, skip to channel 1 after print X'8B' 100 skip to channel 1 immediately 0 C. Direct Access Device Characteristics 0 The remaining devices simulated by ASSIST-V are direct access 1 14 0 devices, disks and drums. The arrangement of data on the recording 0 surfaces of these devices is the same, as are the majority of commands 0 used to program these devices. 0 The primary unit of data on a direct access device is a track. 0 Figure 1 below shows the form of a track. 0 ---------- ----------- ------- -------- X G | Home | G | Count | G | Key | G | Data | G ---+ XXX 1 | Address| 2 | Area | 2 | Area| 2 | Area | 3 | ---------- ----------- ------- -------- | Index ( ========== Record R0 =========== ) | | +-----------------------------------------------------------------+ | | --------- ------- ------- --------- +-> | Count | G | Key | G | Data| G | Count | ..etc.. ---+ | Area | 2 | Area| 2 | Area| 3 | Area | | --------- ------- ------- --------- | ( ========= Record 1 ========== ) ( === Record 2 ... | | +-----------------------------------------------------------------+ | --------- ------- ------ +-> | Count | G | Key | G |Data| G X | Area | 2 | Area| 2 |Area| 4 XXX --------- ------- ------ ( ======= Last Record ======== ) Index 0 Figure 1: Track Format 0 The form of data on a track is as follows. Data records may be 0 recorded in either of two formats: count-key-data or count-data format. 0 Each of these begins with an 8 byte count area that specifies the 0 cylinder and head number, the record number on the track, and the 0 lengths of the key and data fields of the record. For count-key-data 0 records, a key area is present and the length of the key area is given 0 in the count area. For count-data records, no key area exists, and the 0 key length portion of the count area contains 0. The key (if present) 0 and data portions of a record follow the count field. 1 15 0 Each of the count, key, and data areas is separated from the others 0 by a gap, called a G2 gap, which is 6 bytes long. Each record except R0 0 is separated from the previous record by an 8 byte G3 gap. The last 0 record on the track is followed by a variable-length gap, called the G4 0 gap. This gap must be at least 8 bytes long, and consists of the 0 remaining space on the track. 0 The first record on a track is called R0, or the capacity record. 0 This record is of count-data format, and is accessed by special 0 commands, read R0 and write R0. This record is frequently used to 0 maintain a count of free space remaining on the track. 0 Each track has a mark called the "index point", followed by an 8 0 byte gap and then the address, that indicates the track number and the 0 head number. The home address marks the beginning of the track. 0 Channel 1 supports one disk device, at device address X'101'. The 0 disk has four recording surfaces, each of which contains twenty tracks. 0 The capacity of a track is 1692 bytes, but because of required gap 0 areas, the full 1692 bytes is not available for recorded data. The 0 total capacity of a disk unit, including gap space, is 135,360 bytes. 0 Recorded data is transferred at an approximate rate of 76,800 characters 0 per second. The access mechanism takes approximately 2 msec. per 0 cylinder crossed. 0 Channel 2 supports a fixed-head drum-like device, at address 0 X'201'. The unit has twenty tracks of 2048 bytes each, for a total 0 device capacity of 40,960 bytes. Again, because of gaps, this full area 0 may not be filled with user data. The transfer rate for this device is 0 122,880 bytes per second. There is no head movement. 1 16 0 D. Direct Access Commands 0 Commands on direct access devices fall into five general 0 categories: 0 1. Control commands - TIC (branch within a channel program) and Set File 0 Mask (permit or inhibit writing and head movement) 0 2. Seek - activate a different head and/or move access mechanism to a 0 different track 0 3. Search - compare part of the current record against a specified value 0 in main memory. 0 4. Read - transfer data from the device to main memory 0 5. Write - transfer data from main memory to the device 0 Channel commands that may be used for direct access devices are 0 shown below. 1 17 0 Command Code Command Meaning + _______ _______ _______ X'-8'· TIC branch within channel program X'1F' Set file mask set file mask from specified main storage address X'07' Seek position access mechanism/select head X'08' Seek cylinder position access mechanism X'18' Seek head select head X'29' Search key equal compare next key on track with X'49' Search key high key in main storage X'69' Search key high/equal X'31' Search ID equal compare cylinder/head/record number X'51' Search ID high in next count area on track X'71' Search ID high/equal with values in main storage X'39' Search home address compare cylinder/head number in equal home address on track with value in main storage X'06' Read data read data field of next record X'0E' Read key-data read key-data fields of next record X'12' Read count read count field of next record X'16' Read record R0 read count-key-data fields of R0 X'1E' Read count-key-data read count-key-data fields of next record X'05' Write data write data field of next record X'0D' Write key-data write key-data fields of next record X'15' Write record R0 write count-key-data fields of R0 X'1D' Write count-key-data write count-key-data fields of next record 0 CONTROL COMMANDS 0 TIC The data address field of this instruction specifies the address + ___ 0 of the next CCW to be fetched. Program check condition is raised if an 0 invalid address is specified (not a doubleword boundary) or if one TIC 0 chains to another. Bits 0-3 and 32-63 are ignored. If a command is 0 data chained to a TIC, the TIC specifies the address of a CCW whose data 0 address, flags and count are used with the operation code of the old 0 instruction; if a command is command chained to a TIC, the TIC specifies _________________________ · First 4 bits of TIC command code ignored. 1 18 0 the address of a CCW whose full operation code, flags, data address and 0 count are used. 0 Set File Mask The data address of this command identifies one byte in + _____________ 0 main storage. The bits of that byte are used to set write and head 0 movement inhibitions. 0 Mask Meaning + ____ _______ B'000xxx0x' inhibit write R0 B'010xxx0x' inhibit all write commands B'100xxx0x' inhibit format writes (write R0 and write count-key-data) B'110xxx0x' permit all writes B'xx000x0x' permit all seek commands B'xx001x0x' permit seek cylinder and seek head B'xx010x0x' permit seek head B'xx011x0x' inhibit all seek commands 0 Notice that bits 2 and 6 must be zero, or unit check condition is 0 raised. Set file mask is allowed only once within a CCW chain. Initial 0 setting of the file mask is B'00000000'. 0 SEEKS 0 Seek commands are used to position the access mechanism to a 0 desired cylinder and to activate the desired head. Seek commands are 0 limited by the current file mask in effect (see the Set File Mask 0 instruction). The commands normally transfer a 6 byte field specifying 0 cylinder and head number as follows: 0 X'00 00 00 CC 00 HH' 0 where CC identifies the cylinder and HH identifies the head. CC and HH 0 must not exceed the sizes for the device; if they do, or if any of the 0 other bytes is nonzero, the seek is aborted and unit check condition is 0 raised. A CCW count of 6 is normal. If a count greater than 6 is 0 specified, only the first 6 bytes at the specified address are used; if 1 19 0 a count less than 6 is specified, unit check condition is raised. 0 Seek positions access mechanism and selects head. + ____ 0 Seek Cylinder positions access mechanism without head selection. The + _____________ 0 full seek address (both cylinder and head number) must be valid; 0 however, only the cylinder addess is used. 0 Seek Head activates a head without moving the access mechanism. The + _________ 0 full seek address (both cylinder and head number) must be valid; 0 however, only the head number is used. 0 SEARCHES 0 Search commands cause comparison between recorded information on a 0 device and infomation from main storage. The address field of the CCW 0 specifies the main storage address of the field to be compared; the 0 count field in the CCW determines the length to be compared. The 0 comparison is logical, proceeding one byte at a time, left to right. 0 If the search succeeds (i.e., the data on the device is equal to Ä 0 or higher than, as requested Ä the data in main memory), the status 0 modifier bit is set in the CSW. If command chaining is in effect, the 0 status modifier causes one CCW to be skipped. (The next CCW fetched for 0 execution is at the address 16 bytes higher than that of the search 0 CCW.) 0 If the search fails and command chaining is in effect, the 0 immediately following CCW is executed next. This CCW is often a TIC 0 back to the search to force comparison to subsequent records on the same 0 track. However, if the index point of the track is sensed twice in such 1 20 0 a sequence of searches, the command sequence is halted, with the CSW 0 showing device end and channel end. (Two index points guarantee at 0 least one full revolution of the device.) 0 A mode of search called "multitrack searching" may also be 0 specified. This is specified by setting the leftmost bit of the command 0 code "1"; i.e., X'A9' is the multitrack mode of the search key equal 0 command, which normally has code X'29'. In multitrack mode each time 0 the index point is sensed, the next higher numbered head is selected. 0 When no higher numbered head exists, the search terminates with channel 0 end and device end. Using multitrack searches, it is possible to 0 compare all records on a cylinder, instead of on only one track. 0 The search CCW may have a count field longer than the data recorded 0 on the track. Only the number of bytes existing on the track are 0 compared, however; those bytes compared from main storage are the first 0 ones from the area. 0 The search may have a count field shorter than the data recorded on 0 the track. In this case only the number of bytes in the CCW are 0 compared. Action occurs as for full length comparisons. However, write 0 commands that need to be chained from a successful search may be chained 0 only from a search which compared the full field of data recorded on the 0 device. 0 Search Key compares an area in main storage with the next key on the + __________ 0 track. The length is either the length in the CCW or the length of the 0 actual key field, whichever is shorter. Search succeeds if the key on 0 the track is equal to, higher than, or higher than or equal to the key 0 in main storage. 1 21 0 Search ID compares a five byte area in main storage with the cylinder, + _________ 0 head, and record number of count field of next record. The main storage 0 area should contain 0 X'00 CC 00 HH RR' 0 where CC is the cylinder number, HH is the head number, and RR is the 0 record number. Search succeeds if the count field on the track is equal 0 to, higher than, or higher than or equal to the data in main storage. 0 Search Home Address compares a four byte area in main storage with the + ___________________ 0 cylinder and head number of the current track, as written in the home 0 address record. Thus, an implicit positioning of the device to the home 0 address of the track occurs. The main storage area should contain data 0 of the form 0 X'00 CC 00 HH' 0 where CC is the cylinder number and HH is the head number. Search 0 succeeds if the home address on the track is equal to, higher than, or 0 higher than or equal to the data in main storage. 0 READS 0 Reads transfer data from direct access device to main memory. The 0 maximum amount of data transferred is the smaller of the amount 0 specified in the CCW count field and the amount specified in the key 0 length/data length on the track. Any record for which the key length 0 and data length fields are both zero is recognized as an end-of-file 0 record. Reading such a record raises a unit exception condition. 0 Read R0 transfers count, key and data areas of R0. This command causes + _______ 0 positioning to the R0 record. 1 22 0 Read Count transfers the count field of any record (except R0) from + __________ 0 disk to main memory. The normal length for this command is eight. The 0 information passed is of the following form. 0 X'00 CC 00 HH RR KL DD LL' 0 where CC is the cylinder number, HH is the head number, RR is the record 0 number, KL is the key length, and DD LL is the data length field. 0 Read Count-Key-Data transfers all fields of the next record encountered + ___________________ 0 on the track. 0 Read Data transfers the next data field encountered on the track. + _________ 0 Read Key-Data transfers the next key and data fields encountered on the + _____________ 0 track. If the key length is zero, the command operates as a Read Data 0 command. 0 WRITES 0 Write commands are of two groups: format writes and nonformat 0 writes. Format writes are ones in which the count field is rewritten. 0 Format writes rewrite the specified record; furthermore, the entire rest 0 of the track is filled with 0's. The CCW count for a format write must 0 be at least 8. 0 Nonformat writes do not modify the count field on the device. 0 Thus, the key length and data length portions of the record are 0 unchanged, and must represent the true key length and record length of 0 the rewritten record. For this reason if the key length or data length 0 is longer on the track than the amount of data indicated in the CCW 0 count field, the remaining area on the track within the current record 1 23 0 is padded with 0's. If the key length or data length on the track is 0 smaller than the amount of data indicated in the count of the CCW, only 0 the amount of data specified in the count field on the track is written. 0 For positioning reasons, certain chaining requirements are shown. 0 The search command from which the write is chained must examine the full 0 area that it compares; it may not have a CCW length field smaller than 0 the length of the ID or key that is being examined. Also the setting of 0 the file mask must permit the type of write being done. These must be 0 met, or the command will be rejected and a unit check condition will be 0 raised. 0 Write Data updates the next data field encountered on the track. This + __________ 0 command must be chained from a successful Search ID Equal or Search Key 0 Equal command. 0 Write Key and Data updates the next key and data fields encountered on + __________________ 0 the track. This command must be chained from a successful Search ID 0 Equal command. 0 Write R0 specifies that a count, key, and data record for R0 is to be + ________ 0 written. This command must be chained from a successful Search Home 0 Address Equal command. The count in the CCW must be at least 8. 0 Write Count Key Data specifies that a count, a key and a data field are + ____________________ 0 to be written on the track. Any information following the record 0 written is lost, for the entire remainder of the track is filled with 0 0's. The command must be chained from a successful Write R0, Write 0 Count Key Data, Search ID Equal or Search Key Equal. However, a Read 0 Data or Read Key and Data command may be inserted between the search CCW 1 24 0 and the Write Count Key Data. 0 REFERENCES 0 [1] --- ASSIST System Distribution Writeup [2] Hughes and Pfleeger, ASSIST-V: An Environment Simulator for IBM 360 Systems Software Development. [3] Hughes and Pfleeger, ASSIST-V PLM. [4] IBM, S/360 Principles of Operation. [5] Mashey, ASSIST Introductory Assembler User's Manual. [6] Mashey, ASSIST PLM.